The Mill CPU Architecture - the Belt (2 of 13)

This is reminiscent of the Mill CPU which had temporal addressing and called the history a “belt”. the Mill was described in an excellent series of talks: [VIDEO]

The Mill CPU [1] that was discussed a while ago is quite close to being the perfect architecture for a Lisp though, so hopefully many of other parts of these ideas will also come back in even more impressive forms. [1] [VIDEO]

The studies would vary over time because CPU design and bottle necks have changed. Early designs were of course limited by transistor count, now we have OoOe and physical registers are limited by muxers and latency (see the presentations by the mill CPU guy [1] Saving registers in functions is mostly irrelevant - you only save what you'd use, so saving more means fewer spills within the function. Saving on context switches (interrupts alone aren't a big deal) was indeed a problem back when AltiVec was designed, thus it has a special register to keep track of which registers need to be saved. In modern designs this is less of a problem, between higher frequencies, multiple cores, and the other effects of a context switch dominating (effective flush of l1 cache and predictors). The interesting bits nowadays are that load/store is expensive power-wise, which was what ARM identified as the major motivation behind having 32 registers (fewer spills in functions) and OoOe designs. [1] [VIDEO]

How far has development come with the Mill CPU? This video[1] mentions that "nothing with pins on the bottom" has been made yet. [1] [VIDEO]

No ordinary registers. Instead you have a FIFO queue( belt ), where every element( register ) is accessible and has a relative address( offset ). [VIDEO]

False. Mill does not do register renaming. ( Or use "lies". I failed to comprehend you second sentence. ) Here is a talk from one of the designers explaining how it is done: [VIDEO]

According to the CTO, 80% of software operations are loops ( [VIDEO] )? I need convincing of that before I watch the rest of the talk. I suspect it would be a fundamental premise for the architecture of the chip. If it's not true, the stats are probably skewed for an unusual benchmark.